midware_clock_manager.c

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// Framework Includes
#include <driver_clkctrl.h>
#include <midware_clock_manager.h>
 
// Device-specific Includes
#include <xc.h>
 
// Function prototypes
static uint8_t DetermineDivRegVal(clkFrqDiv_t divVal);
 
errFlag_t MW_GetClearClockCfd0Error(void)
{
    const uint8_t regVal       = CLKCTRL_ReadIntFlags();
    const uint8_t cfd0FlagMask = (uint8_t)CLKCTRL_CFD0_bm;
    const bool isCfd0Error     = ((regVal & cfd0FlagMask) == cfd0FlagMask);
 
    errFlag_t flag = NO_ERROR;
    if (isCfd0Error)
    {
        flag = ERROR;
        CLKCTRL_WriteIntFlags(cfd0FlagMask); // The flag is cleared by writing the flag bitmask
    }
 
    return flag;
}
 
errFlag_t MW_GetClearClockCfd1Error(void)
{
    const uint8_t regVal       = CLKCTRL_ReadIntFlags();
    const uint8_t cfd1FlagMask = (uint8_t)CLKCTRL_CFD1_bm;
    const bool isCfd1Error     = ((regVal & cfd1FlagMask) == cfd1FlagMask);
 
    errFlag_t flag = NO_ERROR;
    if (isCfd1Error)
    {
        flag = ERROR;
        CLKCTRL_WriteIntFlags(cfd1FlagMask); // The flag is cleared by writing the flag bitmask
    }
 
    return flag;
}
 
errFlag_t MW_GetClearClockCfm0Error(void)
{
    const uint8_t regVal       = CLKCTRL_ReadIntFlags();
    const uint8_t cfm0FlagMask = (uint8_t)CLKCTRL_CFM0_bm;
    const bool isCfm0Error     = ((regVal & cfm0FlagMask) == cfm0FlagMask);
 
    errFlag_t flag = NO_ERROR;
    if (isCfm0Error)
    {
        flag = ERROR;
        CLKCTRL_WriteIntFlags(cfm0FlagMask); // The flag is cleared by writing the flag bitmask
    }
 
    return flag;
}
 
errFlag_t MW_GetClearClockCfm1Error(void)
{
    const uint8_t regVal       = CLKCTRL_ReadIntFlags();
    const uint8_t cfm1FlagMask = (uint8_t)CLKCTRL_CFM1_bm;
    const bool isCfm1Error     = ((regVal & cfm1FlagMask) == cfm1FlagMask);
 
    errFlag_t flag = NO_ERROR;
    if (isCfm1Error)
    {
        flag = ERROR;
        CLKCTRL_WriteIntFlags(cfm1FlagMask); // The flag is cleared by writing the flag bitmask
    }
 
    return flag;
}
 
void MW_ClearClockCfmDoneFlags(void)
{
    const uint8_t cfmd0FlagMask = (uint8_t)CLKCTRL_CFMD0_bm;
    const uint8_t cfmd1FlagMask = (uint8_t)CLKCTRL_CFMD1_bm;
    CLKCTRL_WriteIntFlags(cfmd0FlagMask | cfmd1FlagMask); // Clear flags by writing flags bitmask
}
 
errFlag_t MW_SetMainClockFrequency(clkFrq_t frequency, clkFrqDiv_t divider)
{
    // Check for invalid inputs
    const bool invalidDiv = (divider == CLK_FRQ_DIV_INVALID1) || (divider == CLK_FRQ_DIV_INVALID2);
    const bool invalidFrq = (frequency == CLK_FRQ_INVALID);
    const bool outOfRange = (divider >= CLK_FRQ_DIV_MAX) || (frequency >= CLK_FRQ_MAX);
 
    if (invalidDiv || invalidFrq || outOfRange)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Set FRQSEL config without changing of RUNSTDBY and AUTOTUNE settings
    const uint8_t frequencySelMask = (uint8_t)CLKCTRL_FRQSEL_gm;
    const uint8_t frequencyConfig  = ((uint8_t)frequency << CLKCTRL_FRQSEL_gp);
    CLKCTRL_ModifyOscHfControlA(frequencySelMask, frequencyConfig);
 
    // Set OSCHF as clock source
    const uint8_t clockSelMask   = (uint8_t)CLKCTRL_CLKSEL_gm;
    const uint8_t clockSelConfig = ((uint8_t)CLKCTRL_CLKSEL_OSCHF_gc);
    CLKCTRL_ModifyMainControlA(clockSelMask, clockSelConfig);
 
    // Set clock division
    const uint8_t regVal = DetermineDivRegVal(divider);
    CLKCTRL_WriteMainControlB(regVal);
 
    return NO_ERROR;
}
 
errFlag_t MW_StartCfd0(cfdSource_t src, cfdReference_t ref)
{
    // Check for invalid inputs
    const bool outOfRange = (src >= CFD_SRC_MAX) || (ref >= CFD_REF_MAX);
 
    if (outOfRange)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Assemble register value
    const uint8_t clockSource    = (uint8_t)src << (uint8_t)CLKCTRL_CFDSRC_gp;
    const uint8_t clockReference = (uint8_t)ref << (uint8_t)CLKCTRL_CFDREF_gp;
    const uint8_t cfdEnable      = (uint8_t)CLKCTRL_CFDEN_bm;
    const uint8_t regVal         = (clockSource | clockReference | cfdEnable);
 
    // Set CFD configuration
    CLKCTRL_WriteCfd0ControlA(regVal);
 
    return NO_ERROR;
}
 
errFlag_t MW_StartCfd1(cfdSource_t src, cfdReference_t ref)
{
    // Check for invalid inputs
    const bool outOfRange = (src >= CFD_SRC_MAX) || (ref >= CFD_REF_MAX);
 
    if (outOfRange)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Assemble register value
    const uint8_t clockSource    = (uint8_t)src << (uint8_t)CLKCTRL_CFDSRC_gp;
    const uint8_t clockReference = (uint8_t)ref << (uint8_t)CLKCTRL_CFDREF_gp;
    const uint8_t cfdEnable      = (uint8_t)CLKCTRL_CFDEN_bm;
    const uint8_t regVal         = (clockSource | clockReference | cfdEnable);
 
    // Set CFD configuration
    CLKCTRL_WriteCfd1ControlA(regVal);
 
    return NO_ERROR;
}
 
errFlag_t MW_StartCfm0(cfmSource_t src, cfmReference_t ref, cfmWindow_t window, bool useContinuous)
{
    // Check for invalid inputs
    const bool outOfRange = (src >= CFM_SRC_MAX) || (ref >= CFM_REF_MAX);
 
    if (outOfRange)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Assemble register value for source
    uint8_t type = (uint8_t)CLKCTRL_TYPE_ONESHOT_gc;
    if (useContinuous)
    {
        type = (uint8_t)CLKCTRL_TYPE_CONTINUOUS_gc;
    }
 
    // Configure window parameters
    CLKCTRL_WriteCfm0RefNum(window.refCount);
    CLKCTRL_WriteCfm0WindowLow(window.windowLow);
    CLKCTRL_WriteCfm0WindowHigh(window.windowHigh);
 
    const uint8_t refEnableMask   = (uint8_t)CLKCTRL_REFCEN_bm;
    const uint8_t referenceConfig = (uint8_t)ref << CLKCTRL_CFMREF_gp;
    const uint8_t regValRef       = (referenceConfig | refEnableMask);
    CLKCTRL_WriteCfm0ControlB(regValRef);
 
    const uint8_t cfmEnableMask = (uint8_t)CLKCTRL_MEN_bm;
    const uint8_t sourceConfig  = (uint8_t)src << CLKCTRL_CFMSRC_gp;
    const uint8_t regValSrc     = (type | sourceConfig | cfmEnableMask);
    CLKCTRL_WriteCfm0ControlA(regValSrc);
 
    return NO_ERROR;
}
 
errFlag_t MW_StartCfm1(cfmSource_t src, cfmReference_t ref, cfmWindow_t window, bool useContinuous)
{
    // Check for invalid inputs
    const bool outOfRange = (src >= CFM_SRC_MAX) || (ref >= CFM_REF_MAX);
 
    if (outOfRange)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Assemble register value for source
    uint8_t type = (uint8_t)CLKCTRL_TYPE_ONESHOT_gc;
    if (useContinuous)
    {
        type = (uint8_t)CLKCTRL_TYPE_CONTINUOUS_gc;
    }
 
    // Configure window parameters
    CLKCTRL_WriteCfm1RefNum(window.refCount);
    CLKCTRL_WriteCfm1WindowLow(window.windowLow);
    CLKCTRL_WriteCfm1WindowHigh(window.windowHigh);
 
    const uint8_t refEnableMask   = (uint8_t)CLKCTRL_REFCEN_bm;
    const uint8_t referenceConfig = (uint8_t)ref << CLKCTRL_CFMREF_gp;
    const uint8_t regValRef       = (referenceConfig | refEnableMask);
    CLKCTRL_WriteCfm1ControlB(regValRef);
 
    const uint8_t cfmEnableMask = (uint8_t)CLKCTRL_MEN_bm;
    const uint8_t sourceConfig  = (uint8_t)src << CLKCTRL_CFMSRC_gp;
    const uint8_t regValSrc     = (type | sourceConfig | cfmEnableMask);
    CLKCTRL_WriteCfm1ControlA(regValSrc);
 
    return NO_ERROR;
}
 
void MW_EnableClockInterrupts(void)
{
    const uint8_t cfdErrorMask = (uint8_t)CLKCTRL_CFD0_bm | (uint8_t)CLKCTRL_CFD1_bm;
    const uint8_t cfmErrorMask = (uint8_t)CLKCTRL_CFM0_bm | (uint8_t)CLKCTRL_CFM1_bm;
 
    CLKCTRL_WriteIntControl(cfdErrorMask | cfmErrorMask);
}
 
static uint8_t DetermineDivRegVal(clkFrqDiv_t divVal)
{
    // Disable prescaler division by default
    const uint8_t divDisableMask   = 0U << CLKCTRL_PEN_bp;
    const uint8_t defaultDivConfig = (uint8_t)CLKCTRL_PDIV_DIV2_gc;
    uint8_t regVal                 = defaultDivConfig | divDisableMask;
 
    if (divVal != CLK_FRQ_DIV_OFF)
    {
        const uint8_t divConfig     = ((uint8_t)divVal << CLKCTRL_PDIV_gp);
        const uint8_t divEnableMask = (uint8_t)CLKCTRL_PEN_bm;
        regVal                      = divConfig | divEnableMask;
    }
 
    return regVal;
}