midware_memory_manager_diag.c

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// Standard Library Includes
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
 
// Framework Includes
#include <driver_cpuctrl.h>
#include <driver_errctrl.h>
#include <driver_nvmctrl.h>
#include <driver_ramctrl.h>
#include <midware_memory_manager_diag.h>
#include <midware_memory_manager_diag_asm.h>
#include <midware_shared_diag_private.h>
 
// Device-specific Includes
#include <xc.h>
 
// RAM variable to reserve address used for memory reads
static volatile uint8_t tempDiagData = 0U;
 
// Error Controller bitmasks used when reading the error channel register
static const uint32_t buserrChMask = 1UL << ERRCTRL_ESF_1_bp;
static const uint32_t ram2ChMask   = 1UL << ERRCTRL_ESF_2_bp;
static const uint32_t flash2ChMask = 1UL << ERRCTRL_ESF_3_bp;
static const uint32_t opcChMask    = 1UL << ERRCTRL_ESF_4_bp;
static const uint32_t ram1ChMask   = 1UL << ERRCTRL_ESF_6_bp;
static const uint32_t flash1ChMask = 1UL << ERRCTRL_ESF_7_bp;
static const uint32_t eepromChMask = 1UL << ERRCTRL_ESF_14_bp;
 
// Private function prototypes
static void DisableRamParityChannels(void);
static void RestoreRamParityChannels(uint8_t buserrCfg);
static void DisableNvmParityChannels(void);
static void RestoreNvmParityChannels(uint8_t buserrCfg, uint8_t opcCfg);
 
static bool InjectCpuDataParityErrorOnRam(void);
static bool InjectCpuAddressParityErrorOnRam(void);
static bool InjectCpuControlParityErrorOnRam(void);
static bool InjectNvmDataParityErrorOnCpu(void);
static bool InjectNvmInstrParityErrorOnCpu(void);
static bool InjectCpuDataParityErrorOnNvm(void);
static bool InjectCpuAddressParityErrorOnNvm(void);
static bool InjectCpuControlParityErrorOnNvm(void);
 
static void DisableRamEccChannels(void);
static void RestoreRamEccChannels(uint8_t buserrCfg, uint8_t ram1Cfg, uint8_t ram2Cfg);
static void DisableFlashEccChannels(void);
static void RestoreFlashEccChannels(uint8_t buserrCfg, uint8_t flash1Cfg, uint8_t flash2Cfg);
static void DisableEepromEccChannels(void);
static void RestoreEepromEccChannels(uint8_t buserrCfg, uint8_t eepromCfg);
 
static bool InjectEccCompErrorOnRam(void);
static bool InjectEcc1ErrorOnRam(void);
static bool InjectEcc2ErrorOnRam(void);
static bool InjectEccCompErrorOnFlash(void);
static bool InjectEcc1ErrorOnFlash(void);
static bool InjectEcc2ErrorOnFlash(void);
static bool InjectEcc1ErrorOnEeprom(void);
static bool InjectEcc2ErrorOnEeprom(void);
 
errFlag_t MW_DiagRamParity(void)
{
    // Check if there are any unhandled errors and ensure the Error Controller is in NORMAL state
    const uint32_t errorChMask = buserrChMask;
    const bool isConfigurable  = IsErrChConfigurable(errorChMask);
    if (!isConfigurable)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Disable and backup global interrupts configuration
    AtomicSectionStart();
 
    // The error injection will trigger a Non-maskable Interrupt (NMI) unless temporarily disabled
    CPUCTRL_SetControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Prevent error injection from triggering a real error response
    uint8_t buserrChBackup = ERRCTRL_ReadConfigBuserr();
    DisableRamParityChannels(); // Disables float and sets channel to NOTIFICATION
 
    // Perform error injections to test each RAM parity checker
    const bool isCpuDataDiagPassed = InjectCpuDataParityErrorOnRam();
    const bool isCpuAddrDiagPassed = InjectCpuAddressParityErrorOnRam();
    const bool isCpuCtrlDiagPassed = InjectCpuControlParityErrorOnRam();
    const bool isDiagPassed = (isCpuDataDiagPassed && isCpuAddrDiagPassed && isCpuCtrlDiagPassed);
 
    RestoreRamParityChannels(buserrChBackup);
 
    // Re-enable NMI
    CPUCTRL_ClearControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Restore global interrupts configuration
    AtomicSectionEnd();
 
    errFlag_t diagResult = ERROR;
    if (isDiagPassed)
    {
        diagResult = NO_ERROR;
    }
    return diagResult;
}
 
errFlag_t MW_DiagNvmParity(void)
{
    // Check if there are any unhandled errors and ensure the Error Controller is in NORMAL state
    const uint32_t errorChMask = buserrChMask | opcChMask;
    const bool isConfigurable  = IsErrChConfigurable(errorChMask);
    if (!isConfigurable)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Disable and backup global interrupts configuration
    AtomicSectionStart();
 
    // The error injection will trigger a Non-maskable Interrupt (NMI) unless temporarily disabled
    CPUCTRL_SetControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Prevent error injection from triggering a real error response
    const uint8_t buserrChBackup = ERRCTRL_ReadConfigBuserr();
    const uint8_t opcChBackup    = ERRCTRL_ReadConfigOpc();
    DisableNvmParityChannels(); // Disables float and sets channels to NOTIFICATION
 
    // Perform error injections to test each NVM and CPU parity checker
    const bool isNvmDataDiagPassed  = InjectNvmDataParityErrorOnCpu();
    const bool isNvmInstrDiagPassed = InjectNvmInstrParityErrorOnCpu();
    const bool isNvmDiagPassed      = isNvmDataDiagPassed && isNvmInstrDiagPassed;
 
    const bool isCpuDataDiagPassed = InjectCpuDataParityErrorOnNvm();
    const bool isCpuAddrDiagPassed = InjectCpuAddressParityErrorOnNvm();
    const bool isCpuCtrlDiagPassed = InjectCpuControlParityErrorOnNvm();
    const bool isCpuDiagPassed
        = (isCpuDataDiagPassed && isCpuAddrDiagPassed && isCpuCtrlDiagPassed);
 
    const bool isDiagPassed = (isNvmDiagPassed && isCpuDiagPassed);
 
    RestoreNvmParityChannels(buserrChBackup, opcChBackup);
 
    // Re-enable NMI
    CPUCTRL_ClearControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Restore global interrupts configuration
    AtomicSectionEnd();
 
    errFlag_t diagResult = ERROR;
    if (isDiagPassed)
    {
        diagResult = NO_ERROR;
    }
    return diagResult;
}
 
errFlag_t MW_DiagRamEcc(void)
{
    // Check if there are any unhandled errors and ensure the Error Controller is in NORMAL state
    const uint32_t errorChMask = buserrChMask | ram1ChMask | ram2ChMask;
    const bool isConfigurable  = IsErrChConfigurable(errorChMask);
    if (!isConfigurable)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Disable and backup global interrupts configuration
    AtomicSectionStart();
 
    // The error injection will trigger a Non-maskable Interrupt (NMI) unless temporarily disabled
    CPUCTRL_SetControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Prevent error injection from triggering a real error response
    const uint8_t buserrChBackup = ERRCTRL_ReadConfigBuserr();
    const uint8_t ram1ChBackup   = ERRCTRL_ReadConfigRam1();
    const uint8_t ram2ChBackup   = ERRCTRL_ReadConfigRam2();
    DisableRamEccChannels(); // Disables float and sets channels to NOTIFICATION
 
    // Perform error injections to test each RAM ECC checker
    const bool isCompDiagPassed = InjectEccCompErrorOnRam();
    const bool isEcc1DiagPassed = InjectEcc1ErrorOnRam();
    const bool isEcc2DiagPassed = InjectEcc2ErrorOnRam();
    const bool isDiagPassed     = (isCompDiagPassed && isEcc1DiagPassed && isEcc2DiagPassed);
 
    RestoreRamEccChannels(buserrChBackup, ram1ChBackup, ram2ChBackup);
 
    // Re-enable NMI
    CPUCTRL_ClearControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Restore global interrupts configuration
    AtomicSectionEnd();
 
    errFlag_t diagResult = ERROR;
    if (isDiagPassed)
    {
        diagResult = NO_ERROR;
    }
    return diagResult;
}
 
errFlag_t MW_DiagNvmFlashEcc(void)
{
    // Check if there are any unhandled errors and ensure the Error Controller is in NORMAL state
    const uint32_t errorChMask = buserrChMask | flash1ChMask | flash2ChMask;
    const bool isConfigurable  = IsErrChConfigurable(errorChMask);
    if (!isConfigurable)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Disable and backup global interrupts configuration
    AtomicSectionStart();
 
    // The error injection will trigger a Non-maskable Interrupt (NMI) unless temporarily disabled
    CPUCTRL_SetControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Prevent error injection from triggering a real error response
    const uint8_t buserrChBackup = ERRCTRL_ReadConfigBuserr();
    const uint8_t flash1ChBackup = ERRCTRL_ReadConfigFlash1();
    const uint8_t flash2ChBackup = ERRCTRL_ReadConfigFlash2();
    DisableFlashEccChannels(); // Disables float and sets channels to NOTIFICATION
 
    // Perform error injections to test each NVM ECC checker on Flash
    const bool isCompDiagPassed = InjectEccCompErrorOnFlash();
    const bool isEcc1DiagPassed = InjectEcc1ErrorOnFlash();
    const bool isEcc2DiagPassed = InjectEcc2ErrorOnFlash();
    const bool isDiagPassed     = (isCompDiagPassed && isEcc1DiagPassed && isEcc2DiagPassed);
 
    RestoreFlashEccChannels(buserrChBackup, flash1ChBackup, flash2ChBackup);
 
    // Re-enable NMI
    CPUCTRL_ClearControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Restore global interrupts configuration
    AtomicSectionEnd();
 
    errFlag_t diagResult = ERROR;
    if (isDiagPassed)
    {
        diagResult = NO_ERROR;
    }
    return diagResult;
}
 
errFlag_t MW_DiagNvmEepromEcc(void)
{
    // Check if there are any unhandled errors and ensure the Error Controller is in NORMAL state
    const uint32_t errorChMask = buserrChMask | eepromChMask;
    const bool isConfigurable  = IsErrChConfigurable(errorChMask);
    if (!isConfigurable)
    {
        /* cppcheck-suppress misra-c2012-15.5 */
        return ERROR;
    }
 
    // Disable and backup global interrupts configuration
    AtomicSectionStart();
 
    // The error injection will trigger a Non-maskable Interrupt (NMI) unless temporarily disabled
    CPUCTRL_SetControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Prevent error injection from triggering a real error response
    const uint8_t buserrChBackup = ERRCTRL_ReadConfigBuserr();
    const uint8_t eepromChBackup = ERRCTRL_ReadConfigEeprom();
    DisableEepromEccChannels(); // Disables float and sets channels to NOTIFICATION
 
    // Perform error injections to test each NVM ECC checker on EEPROM
    const bool isEcc1DiagPassed = InjectEcc1ErrorOnEeprom();
    const bool isEcc2DiagPassed = InjectEcc2ErrorOnEeprom();
    const bool isDiagPassed     = (isEcc1DiagPassed && isEcc2DiagPassed);
 
    RestoreEepromEccChannels(buserrChBackup, eepromChBackup);
 
    // Re-enable NMI
    CPUCTRL_ClearControlA((uint8_t)CPU_NMIDIS_bm);
 
    // Restore global interrupts configuration
    AtomicSectionEnd();
 
    errFlag_t diagResult = ERROR;
    if (isDiagPassed)
    {
        diagResult = NO_ERROR;
    }
    return diagResult;
}
 
// Sets the BUSSERR Error Channel to NOTIFICATION severity and disables I/O float
static void DisableRamParityChannels(void)
{
    const uint8_t stateMask       = (uint8_t)ERRCTRL_STATE_gm;
    const uint8_t floatConfig     = 0U << ERRCTRL_FLOAT_bp; // Disable I/O float
    const uint8_t severityConfig  = (uint8_t)ERRCTRL_ERRLVL_NOTIFICATION_gc;
    const uint8_t disableChConfig = (floatConfig | severityConfig);
 
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(disableChConfig);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Restores the BUSERR Error Channel config to its backed up configuration
static void RestoreRamParityChannels(uint8_t buserrCfg)
{
    const uint8_t stateMask = (uint8_t)ERRCTRL_STATE_gm;
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(buserrCfg);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Sets the BUSSERR and OPC Error Channels to NOTIFICATION severity and disables I/O float
static void DisableNvmParityChannels(void)
{
    const uint8_t stateMask       = (uint8_t)ERRCTRL_STATE_gm;
    const uint8_t floatConfig     = 0U << ERRCTRL_FLOAT_bp; // Disable I/O float
    const uint8_t severityConfig  = (uint8_t)ERRCTRL_ERRLVL_NOTIFICATION_gc;
    const uint8_t disableChConfig = (floatConfig | severityConfig);
 
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(disableChConfig);
    ERRCTRL_WriteConfigOpc(disableChConfig);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Restores the BUSERR and OPC Error Channels config to its backed up configuration
static void RestoreNvmParityChannels(uint8_t buserrCfg, uint8_t opcCfg)
{
    const uint8_t stateMask = (uint8_t)ERRCTRL_STATE_gm;
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(buserrCfg);
    ERRCTRL_WriteConfigOpc(opcCfg);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Sets the BUSSERR and RAM1/2 Error Channels to NOTIFICATION severity and disables I/O float
static void DisableRamEccChannels(void)
{
    const uint8_t stateMask       = (uint8_t)ERRCTRL_STATE_gm;
    const uint8_t floatConfig     = 0U << ERRCTRL_FLOAT_bp; // Disable I/O float
    const uint8_t severityConfig  = (uint8_t)ERRCTRL_ERRLVL_NOTIFICATION_gc;
    const uint8_t disableChConfig = (floatConfig | severityConfig);
 
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(disableChConfig);
    ERRCTRL_WriteConfigRam1(disableChConfig);
    ERRCTRL_WriteConfigRam2(disableChConfig);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Restores the BUSERR and RAM1/2 Error Channels config to its backed up configuration
static void RestoreRamEccChannels(uint8_t buserrCfg, uint8_t ram1Cfg, uint8_t ram2Cfg)
{
    const uint8_t stateMask = (uint8_t)ERRCTRL_STATE_gm;
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(buserrCfg);
    ERRCTRL_WriteConfigRam1(ram1Cfg);
    ERRCTRL_WriteConfigRam2(ram2Cfg);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Sets the BUSSERR and FLASH1/2 Error Channels to NOTIFICATION severity and disables I/O float
static void DisableFlashEccChannels(void)
{
    const uint8_t stateMask       = (uint8_t)ERRCTRL_STATE_gm;
    const uint8_t floatConfig     = 0U << ERRCTRL_FLOAT_bp; // Disable I/O float
    const uint8_t severityConfig  = (uint8_t)ERRCTRL_ERRLVL_NOTIFICATION_gc;
    const uint8_t disableChConfig = (floatConfig | severityConfig);
 
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(disableChConfig);
    ERRCTRL_WriteConfigFlash1(disableChConfig);
    ERRCTRL_WriteConfigFlash2(disableChConfig);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Restores the BUSERR and FLASH1/2 Error Channels config to its backed up configuration
static void RestoreFlashEccChannels(uint8_t buserrCfg, uint8_t flash1Cfg, uint8_t flash2Cfg)
{
    const uint8_t stateMask = (uint8_t)ERRCTRL_STATE_gm;
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(buserrCfg);
    ERRCTRL_WriteConfigFlash1(flash1Cfg);
    ERRCTRL_WriteConfigFlash2(flash2Cfg);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Sets the BUSSERR and EEPROM Error Channels to NOTIFICATION severity and disables I/O float
static void DisableEepromEccChannels(void)
{
    const uint8_t stateMask       = (uint8_t)ERRCTRL_STATE_gm;
    const uint8_t floatConfig     = 0U << ERRCTRL_FLOAT_bp; // Disable I/O float
    const uint8_t severityConfig  = (uint8_t)ERRCTRL_ERRLVL_NOTIFICATION_gc;
    const uint8_t disableChConfig = (floatConfig | severityConfig);
 
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(disableChConfig);
    ERRCTRL_WriteConfigEeprom(disableChConfig);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
// Restores the BUSERR and EEPROM Error Channels config to its backed up configuration
static void RestoreEepromEccChannels(uint8_t buserrCfg, uint8_t eepromCfg)
{
    const uint8_t stateMask = (uint8_t)ERRCTRL_STATE_gm;
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_CONFIG_gc);
    ERRCTRL_WriteConfigBuserr(buserrCfg);
    ERRCTRL_WriteConfigEeprom(eepromCfg);
    ERRCTRL_ModifyControlA(stateMask, (uint8_t)ERRCTRL_STATE_NORMAL_gc);
}
 
static bool InjectCpuDataParityErrorOnRam(void)
{
    // Inject and trigger data parity error
    ASM_InjectCpuDataParityRam();
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_PARITYD_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectCpuAddressParityErrorOnRam(void)
{
    // Inject and trigger address parity error
    ASM_InjectCpuAddressParityRam();
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_PARITYA_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectCpuControlParityErrorOnRam(void)
{
    // Inject and trigger control parity error
    ASM_InjectCpuControlParityRam();
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_PARITYC_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectNvmDataParityErrorOnCpu(void)
{
    // Inject and trigger data parity error
    /* cppcheck-suppress misra-c2012-11.4 */
    ASM_InjectNvmDataParity((uint8_t*)DIAG_FLASH_ADDRESS);
 
    // Check if all correct flags are set after injection
    const uint8_t cpuIntFlags     = CPUCTRL_ReadIntFlags();
    const uint8_t cpuParityMask   = (uint8_t)CPU_PARITYD_bm;
    const bool isCpuDataParitySet = ((cpuIntFlags & cpuParityMask) == cpuParityMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isCpuDataParitySet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuParityMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectNvmInstrParityErrorOnCpu(void)
{
    // Inject and trigger data parity error
    ASM_InjectNvmInstructionParity();
 
    // Check if all correct flags are set after injection
    const uint8_t cpuIntFlags            = CPUCTRL_ReadIntFlags();
    const uint8_t cpuParityMask          = (uint8_t)CPU_PARITYI_bm;
    const bool isCpuInstructionParitySet = ((cpuIntFlags & cpuParityMask) == cpuParityMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & opcChMask) == opcChMask);
 
    const bool isDiagPassed = (isCpuInstructionParitySet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuParityMask);
    ERRCTRL_WriteChannelStatus(opcChMask);
 
    return isDiagPassed;
}
 
static bool InjectCpuDataParityErrorOnNvm(void)
{
    // Inject and trigger data parity error
    /* cppcheck-suppress misra-c2012-11.4 */
    ASM_InjectCpuDataParityNvm((uint8_t*)DIAG_EEPROM_ADDRESS);
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmIntMask  = (uint8_t)NVMCTRL_PARITYD_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmIntMask) == nvmIntMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    NVMCTRL_WriteIntFlagsB(nvmIntMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectCpuAddressParityErrorOnNvm(void)
{
    // Inject and trigger data parity error
    /* cppcheck-suppress misra-c2012-11.4 */
    ASM_InjectCpuAddressParityNvm((uint8_t*)DIAG_FLASH_ADDRESS);
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmIntMask  = (uint8_t)NVMCTRL_PARITYA_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmIntMask) == nvmIntMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    NVMCTRL_WriteIntFlagsB(nvmIntMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectCpuControlParityErrorOnNvm(void)
{
    // Inject and trigger data parity error
    /* cppcheck-suppress misra-c2012-11.4 */
    ASM_InjectCpuControlParityNvm((uint8_t*)DIAG_FLASH_ADDRESS);
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmIntMask  = (uint8_t)NVMCTRL_PARITYC_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmIntMask) == nvmIntMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & buserrChMask) == buserrChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    NVMCTRL_WriteIntFlagsB(nvmIntMask);
    ERRCTRL_WriteChannelStatus(buserrChMask);
 
    return isDiagPassed;
}
 
static bool InjectEccCompErrorOnRam(void)
{
    // Inject and trigger ECC comparator error
    ASM_InjectRamEccComp();
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_COMP_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & ram2ChMask) == ram2ChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(ram2ChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc1ErrorOnRam(void)
{
    // Inject and trigger 1-bit ECC error
    tempDiagData = 0x55U;
    ASM_InjectRamEcc1(&tempDiagData);
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_ECC1_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & ram1ChMask) == ram1ChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(ram1ChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc2ErrorOnRam(void)
{
    // Inject and trigger 2-bit ECC error
    tempDiagData = 0x55U;
    ASM_InjectRamEcc2(&tempDiagData);
 
    // Check if all correct flags are set after injection
    const uint8_t ramIntFlags   = RAMCTRL_ReadIntFlags();
    const uint8_t ramParityMask = (uint8_t)RAMCTRL_ECC2_bm;
    const bool isRamFlagSet     = ((ramIntFlags & ramParityMask) == ramParityMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus  = ERRCTRL_ReadChannelStatus();
    const uint32_t errChMask = buserrChMask | ram2ChMask;
    const bool isErrorChSet  = ((chStatus & errChMask) == errChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    RAMCTRL_WriteIntFlags(ramParityMask);
    ERRCTRL_WriteChannelStatus(errChMask);
 
    return isDiagPassed;
}
 
static bool InjectEccCompErrorOnFlash(void)
{
    // Inject ECC comparator error, trigger by reading from Flash.
    NVMCTRL_SetControlD((uint8_t)NVMCTRL_COMP_bm);
    /* cppcheck-suppress misra-c2012-11.4 */
    tempDiagData = *(uint8_t*)DIAG_FLASH_ADDRESS; // No need to check FBUSY flag for Flash read.
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmCompMask = (uint8_t)NVMCTRL_COMP_bm;
    const bool isRamFlagSet   = ((nvmIntFlags & nvmCompMask) == nvmCompMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & flash2ChMask) == flash2ChMask);
 
    const bool isDiagPassed = (isRamFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    NVMCTRL_WriteIntFlagsB(nvmCompMask);
    ERRCTRL_WriteChannelStatus(flash2ChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc1ErrorOnFlash(void)
{
    // Inject 1-bit ECC error, trigger by reading from Flash.
    NVMCTRL_SetControlD((uint8_t)NVMCTRL_ECC1_bm);
    /* cppcheck-suppress misra-c2012-11.4 */
    tempDiagData = *(uint8_t*)DIAG_FLASH_ADDRESS; // No need to check FBUSY flag for Flash read.
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmEccMask  = (uint8_t)NVMCTRL_FECC1_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmEccMask) == nvmEccMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & flash1ChMask) == flash1ChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    NVMCTRL_WriteIntFlagsB(nvmEccMask);
    ERRCTRL_WriteChannelStatus(flash1ChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc2ErrorOnFlash(void)
{
    // Inject 2-bit ECC error, trigger by reading from Flash.
    NVMCTRL_SetControlD((uint8_t)NVMCTRL_ECC2_bm);
    /* cppcheck-suppress misra-c2012-11.4 */
    tempDiagData = *(uint8_t*)DIAG_FLASH_ADDRESS; // No need to check FBUSY flag for Flash read.
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmEccMask  = (uint8_t)NVMCTRL_FECC2_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmEccMask) == nvmEccMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus  = ERRCTRL_ReadChannelStatus();
    const uint32_t errChMask = buserrChMask | flash2ChMask;
    const bool isErrorChSet  = ((chStatus & errChMask) == errChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    NVMCTRL_WriteIntFlagsB(nvmEccMask);
    ERRCTRL_WriteChannelStatus(errChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc1ErrorOnEeprom(void)
{
    // Inject 1-bit ECC error, trigger by reading from EEPROM.
    NVMCTRL_SetControlD((uint8_t)NVMCTRL_ECC1_bm);
    /* cppcheck-suppress misra-c2012-11.4 */
    tempDiagData = *(uint8_t*)DIAG_EEPROM_ADDRESS; // No need to check EEBUSY flag for EEPROM read.
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmEccMask  = (uint8_t)NVMCTRL_EECC1_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmEccMask) == nvmEccMask);
 
    const uint32_t chStatus = ERRCTRL_ReadChannelStatus();
    const bool isErrorChSet = ((chStatus & eepromChMask) == eepromChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    NVMCTRL_WriteIntFlagsB(nvmEccMask);
    ERRCTRL_WriteChannelStatus(eepromChMask);
 
    return isDiagPassed;
}
 
static bool InjectEcc2ErrorOnEeprom(void)
{
    // Inject 2-bit ECC error, trigger by reading from EEPROM.
    NVMCTRL_SetControlD((uint8_t)NVMCTRL_ECC2_bm);
    /* cppcheck-suppress misra-c2012-11.4 */
    tempDiagData = *(uint8_t*)DIAG_EEPROM_ADDRESS; // No need to check EEREADY flag for EEPROM read.
 
    // Check if all correct flags are set after injection
    const uint8_t nvmIntFlags = NVMCTRL_ReadIntFlagsB();
    const uint8_t nvmIntMask  = (uint8_t)NVMCTRL_EECC2_bm;
    const bool isNvmFlagSet   = ((nvmIntFlags & nvmIntMask) == nvmIntMask);
 
    const uint8_t cpuIntFlags   = CPUCTRL_ReadIntFlags();
    const uint8_t cpuBuserrMask = (uint8_t)CPU_BUSERR_bm;
    const bool isCpuFlagSet     = ((cpuIntFlags & cpuBuserrMask) == cpuBuserrMask);
 
    const uint32_t chStatus  = ERRCTRL_ReadChannelStatus();
    const uint32_t errChMask = buserrChMask | eepromChMask;
    const bool isErrorChSet  = ((chStatus & errChMask) == errChMask);
 
    const bool isDiagPassed = (isNvmFlagSet && isCpuFlagSet && isErrorChSet);
 
    // Write to error flags and error channel to clear them
    CPUCTRL_WriteIntFlags(cpuBuserrMask);
    NVMCTRL_WriteIntFlagsB(nvmIntMask);
    ERRCTRL_WriteChannelStatus(errChMask);
 
    return isDiagPassed;
}